? semiconductor components industries, llc, 2001 january, 2001 rev. 7 1 publication order number: cs403/d cs403 5.0 v, 750 ma linear regulator with reset the cs403 is a linear regulator specially designed as a post regulator. the cs403 provides low noise, low drift, and high accuracy to improve the performance of a switching power supply. it is ideal for applications requiring a highly efficient and accurate linear regulator. the active reset makes the device particularly well suited to supply microprocessor based systems. the pnpnpn output stage assures a low dropout voltage without requiring excessive supply current. its features include low dropout (1.0 v typically) and low supply drain (4.0 ma typical with i out = 500 ma). the cs403 design optimizes supply rejection by switching the internal reference from the supply input to the regulator output as soon as the nominal output voltage is reached. features ? 5.0 v 3.0% output voltage ? low drift ? high efficiency ? short circuit protection ? active delayed reset ? noise immunity on reset ? 750 ma output current output current limit + + error amp low voltage inhibit comparator v out delay + reset i charge scr latch delay comparator to v out v in start ref gnd v cmp figure 1. block diagram http://onsemi.com pin connections and marking diagram device package shipping ordering information 50 units/rail cs403gt5 to220* straight 50 units/rail cs403gtva5 to220* vertical 50 units/rail cs403gtha5 to220* horizontal to220 five lead t suffix case 314d 1 5 to220 five lead tva suffix case 314k to220 five lead tha suffix case 314a 1 5 cs403 awlyww 1 tab = gnd pin 1. v in 2. reset 3. gnd 4. delay 5. v out a = assembly location wl, l = wafer lot yy, y = year ww, w = work week 1 *five lead.
cs403 http://onsemi.com 2 absolute maximum ratings* rating value unit forward input voltage 18 v operating junction temperature, t j 40 to 150 c storage temperature range, t s 55 to +150 c lead temperature soldering: wave solder: (through hole styles only) (note 1.) 260 peak c 1. 10 second maximum. *the maximum package power dissipation must be observed. electrical characteristics (refer to the test circuit, 40 c t c 125 c, 40 c t j 150 c, 7.0 v v in 10 v, unless otherwise specified.) characteristic test conditions min typ max unit output voltage, v out v in = 8.5 v, i out = 250 ma, t j = 25 c 100 ma i out 750 ma 4.95 4.85 5.00 5.00 5.05 5.15 v v operating input voltage 100 to 750 ma 0.75 18.0 v load regulation 100 ma i out 750 ma, v in = 8.5 v 30 100 mv dropout voltage i out = 750 ma 1.4 1.8 v quiescent current i out = 0 ma i out = 750 ma 3.0 5.0 4.0 25 ma ma psrr i out 250 ma, f = 120 hz c out = 10 m f, v in = 8.5 v + v pp 70 db output short circuit current 1.0 a reset output voltage i r = 1.6 ma, 1.0 v out 4.75 v 0.08 0.40 v reset output leakage current v out in regulation 0 50 m a delay time for reset output c d = 100 nf 10 20 30 ms reset threshold, v rth v out increasing v out 0.04 v reset threshold, v rtl v out decreasing 4.75 v threshold hysteresis 10 50 mv delay, v dtc charge 3.7 4.0 4.4 v delay, v dtd discharge 3.1 3.5 3.9 v delay hysteresis, v dh 200 500 1000 mv reset delay capacitor charging current, i ch 10 20 40 m a reset delay capacitor discharge voltage, v dis 0.6 1.2 v package pin description package lead # 5 lead to220 lead symbol function 1 v in input voltage. 2 reset cmos compatible output lead. reset goes low whenever v out falls out of regulation. 3 gnd ground connection. 4 delay timing capacitor for reset function. 5 v out regulated output voltage, 5.0 v (typ).
cs403 http://onsemi.com 3 typical performance characteristics figure 2. output voltage vs. v in , i q 0 2.0 4.0 6.0 8.0 10 0 1.5 2.5 3.5 4.5 5.5 22 18 14 10 6.0 0 v out supply current (ma) v in 40 0 40 80 120 150 junction temperature ( c), t j 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 v out (v) v o i q i out = 250 ma figure 3. output voltage vs. junction temperature figure 4. dropout voltage vs. output current over temperature t a = 40 c 1.2 1.0 0.8 0.6 0.4 0.2 0 dropout voltage (v) 0 100 200 300 400 500 output current (ma), i out t a = 25 c reset circuit v rt(on) v rt(off) v out reset delay v dtc v dtd v dh v rl v rh t delay v dis (1) (2) (2) (3) (1) no delay capacitor. (2) with delay capacitor (3) max. reset voltage (< 1.0 v) figure 5. reset circuit waveform
cs403 http://onsemi.com 4 circuit description the cs403 reset function is very precise, has hysteresis on both the reset and delay comparators, a latching delay capacitor discharge circuit, and operates down to 1.0 v. the reset circuit output is an open collector type with on and off parameters as specified. the reset output npn transistor is controlled by the two circuits described (see figure 1). low voltage inhibit circuit this circuit monitors output voltage, and when output voltage is below the specified minimum, causes the reset output transistor to be in the on (saturation) state. when the output voltage is above the specified level, this circuit permits the reset output transistor to go into the off state if allowed by the reset delay circuit. reset delay circuit this circuit provides a programmable (external capacitor) delay on the reset output lead. the delay lead provides source current to the external delay capacitor only when the low voltage inhibit circuit indicates that output voltage is above v rt(on) . otherwise, the delay lead sinks current to ground (used to discharge the delay capacitor). the discharge current is latched on when the output voltage is below v rt(off) , or when the voltage on the delay capacitor is above v dis . in other words, the delay capacitor is fully discharged any time the output voltage falls out of regulation, even for a short period of time. this feature ensures a controlled reset pulse is generated following detection of an error condition. the circuit allows the reset output transistor to go to the off (open) state only when the voltage on the delay lead is higher than v dis . t d c d v dtc i ch c delay 2.10 5 (typical). where: t d = time delay. c d = value of external charging capacitor (see figure 6). v dtc = delay threshold charge. i ch = reset delay capacitor charging current. cs403 v in delay v out reset gnd c 1 * 100 nf c 2 ** c out = 10 m f to 100 m f 100 nf c d figure 6. test circuit c 1 * is required if the regulator is far from the power source filter. c 2 ** is required for stability. application notes stability considerations the output or compensation capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr, can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (25 c to 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provides this information. the value for the output capacitor c out shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. to determine an acceptable value for c out for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. step 1: place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. a decade box connected in series with the capacitor will simulate the
cs403 http://onsemi.com 5 higher esr of an aluminum capacitor. leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. step 2: with the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. if no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. step 3: increase the esr of the capacitor from zero using the decade box and vary the load current until oscillations appear. record the values of load current and esr that cause the greatest oscillation. this represents the worst case load conditions for the regulator at low temperature. step 4: maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. this point represents the worst case input voltage conditions. step 5: if the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. a smaller capacitor will usually cost less and occupy less board space. if the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. step 6: test the load transient response by switching in various loads at several frequencies to simulate its real working environment. vary the esr to reduce ringing. step 7: raise the temperature to the highest specified operating temperature. v ary the load current as instructed in step 5 to test for any oscillations. once the minimum capacitor value with the maximum esr is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. the esr of the capacitor should be less than 50% of the maximum allowable esr found in step 3 above. calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 7) is: p d(max) v in(max) v out(min) i out(max) v in(max) i q (1) where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current, for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r q ja can be calculated: r ja 150 c t a p d (2) the value of r q ja can then be compared with those in the package section of the data sheet. those packages with r q ja 's less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. figure 7. single output regulator with key performance parameters labeled smart regulator control features i out i in i q heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r q ja . r ja r jc r cs r sa (3) where: r q jc = the junctiontocase thermal resistance, r q cs = the casetoheatsink thermal resistance, and r q sa = the heatsinktoambient thermal resistance. r q jc appears in the package section of the data sheet. like r q ja , it is a function of package type. r q cs and r q sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
cs403 http://onsemi.com 6 package dimensions to220 five lead t suffix case 314d04 issue e q 12345 u k d g a b 5 pl j h l e c m q m 0.356 (0.014) t seating plane t dim min max min max millimeters inches a 0.572 0.613 14.529 15.570 b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 g 0.067 bsc 1.702 bsc h 0.087 0.112 2.210 2.845 j 0.015 0.025 0.381 0.635 k 0.990 1.045 25.146 26.543 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 u 0.105 0.117 2.667 2.972 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. to220 five lead tva suffix case 314k01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 10.92 (0.043) maximum. dim min max min max millimeters inches a 0.560 0.590 14.22 14.99 b 0.385 0.415 9.78 10.54 c 0.160 0.190 4.06 4.83 d 0.027 0.037 0.69 0.94 e 0.045 0.055 1.14 1.40 f 0.530 0.545 13.46 13.84 g 0.067 bsc 1.70 bsc j 0.014 0.022 0.36 0.56 k 0.785 0.800 19.94 20.32 l 0.321 0.337 8.15 8.56 m 0.063 0.078 1.60 1.98 q 0.146 0.156 3.71 3.96 s 0.146 0.196 3.71 4.98 u 0.460 0.475 11.68 12.07 w 55 r 0.271 0.321 6.88 8.15 a u d g b t m 0.356 (0.014) m q 5 pl q k f j c e t s l 12345 seating plane r m w
cs403 http://onsemi.com 7 to220 five lead tha suffix case 314a03 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension d does not include interconnect bar (dambar) protrusion. dimension d including protrusion shall not exceed 0.043 (1.092) maximum. dim a min max min max millimeters 0.572 0.613 14.529 15.570 inches b 0.390 0.415 9.906 10.541 c 0.170 0.180 4.318 4.572 d 0.025 0.038 0.635 0.965 e 0.048 0.055 1.219 1.397 f 0.570 0.585 14.478 14.859 g 0.067 bsc 1.702 bsc j 0.015 0.025 0.381 0.635 k 0.730 0.745 18.542 18.923 l 0.320 0.365 8.128 9.271 q 0.140 0.153 3.556 3.886 s 0.210 0.260 5.334 6.604 u 0.468 0.505 11.888 12.827 t seating plane l s e c f k j optional chamfer 5x d 5x m p m 0.014 (0.356) t g a u b q p package thermal data parameter to220 unit r q jc typical 4.1 c/w r q ja typical 50 c/w
cs403 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. cs403/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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